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4G curriculum (older)

For students clearing pending subjects of the 4G scheme (7-digit subject codes, e.g. 4341602). Students admitted under the current scheme study the 5G curriculum.

4353206 · Semester 5 · 4G scheme

VLSI Technology

Notes and solutions following the Gujarat Technological University (GTU) syllabus for 4353206. Independent material — not issued by the university.

Information & Communication Technology

Materials

Syllabus

The official syllabus this material follows.

  • Syllabus

    9 pages

    FreeRead

Complete Book

The whole syllabus, unit by unit, written for the exam.

Problem Solver

Step-by-step solutions to typical problems.

PYQ Solutions

Past university papers, fully solved.

  • Solved past papers — detailed answers

    146 pages · English + ગુજરાતી

    Premium Preview · 34 pages

  • Solved past papers — short answers

    58 pages · English + ગુજરાતી

    Premium Preview · 4 pages

Syllabus units

Unit 1: Introduction to VLSI6 h · 10 marks
  • VLSI design Methodology, Time to Market, Major Constraints for chip designing, ASIC Design flow
  • Y-Chart
  • Concept of Top-Down, Bottom-Up approach
  • Regularity, modularity, locality
  • Overview of FPGA, Gate Array Design, Standard Cell Based Design, Full Custom Design
Unit 2: MOS Transistor8 h · 14 marks
  • Energy band Diagram and Structure of MOS
  • The MOS System under External Bias
  • Channel formation
  • Symbols for different MOSFET
  • MOSFET Current-Voltage characteristics
  • Gradual channel Approximation
  • Needs of scaling
  • Full-Voltage Scaling, Constant-Voltage Scaling
  • Effect of Scaling
Unit 3: MOS Inverters6 h · 12 marks
  • Concept and working of Ideal Inverter
  • Noise Margin
  • Voltage Transfer Characteristics
  • Working and VTC without derivation
  • Working and VTC without derivation for Enhancement & Depletion type MOSFET load
  • Working and VTC without derivation for CMOS inverter
Unit 4: MOS Circuits10 h · 18 marks
  • MOS logic circuits with Depletion nMOS Loads
  • CMOS logic circuits
  • Stick Diagram
  • Euler path Approach
  • Complex logic circuits
  • The SR latch circuit
  • Clocked latch and Flip-flop circuit
  • CMOS D-latch and Edge-triggered flip-flop
Unit 5: Verilog Programming12 h · 16 marks
  • Module definition
  • RTL coding style: Gate level, Data flow, Behavioral, Mixed approach
  • Stimulus generation
  • Basic Logic gate implementation in Verilog
  • Verilog code for adder and subtractor circuits
  • Combinational circuits: Multiplexer, Demultiplexer, Decoder and Encoder, Parity Generator and parity checker
  • Basic Sequential circuits: SR latch, D F/F, T F/F, JK F/F
  • Parallel input Parallel output Shift Register, Up Counter, Down Counter

About this course

This course will provide an opportunity to the ICT students to learn about fundamentals of VLSI Technology such as trends in VLSI, MOSFET structure and Analysis of MOS circuits. In laboratory part of this course, students will be given exposure to develop RTL code for different types of digital circuits. This subject is very important for the students for their career advancement in VLSI field.