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DI05000021 · Semester 5 · 5G scheme

VLSI System

Notes and solutions following the Gujarat Technological University (GTU) syllabus for DI05000021. Independent material — not issued by the university.

Electronics & Communication EngineeringInformation & Communication Technology

Materials

Syllabus

The official syllabus this material follows.

  • Syllabus

    7 pages

    FreeRead

Complete Book

The whole syllabus, unit by unit, written for the exam.

Slides

Lecture slides for revision.

Syllabus units

Unit 1: MOS TRANSISTOR
  • Explain Energy band diagram and structure of MOS
  • MOS system under external bias
  • Symbols for different MOSFET
  • Structure and operation of MOSFET
  • Channel formation
  • Gradual channel Approximation
  • MOSFET Current-Voltage characteristics
  • Needs of scaling
  • Full-Voltage Scaling, Constant-Voltage Scaling
  • Effect of Scaling
  • Dual Gate MOSFET: Concept, Structure, Advantages and Limitations
  • Silicon on Insulator(SOI): Concept, Structure, Advantages and Limitations
  • High-K metal gate MOSFET: Concept, Structure, Advantages and Limitations
  • FIN-FET: Concept, Structure, Advantages and Limitations
  • Gate All Around(GAA) FET: Concept, Structure, Advantages and Limitations
Unit 2: MOS INVERTERS
  • Concept and working of Ideal Inverter
  • Noise Margin and Noise Immunity
  • Voltage Transfer Characteristic of Ideal Inverter
  • Working and VTC of Resistive Load Inverter (without derivation)
  • Working and VTC of Depletion load Inverter (without derivation)
  • Working and VTC of CMOS inverter (without derivation)
Unit 3: MOS CIRCUIT
  • Two Input NAND and NOR Gate with depletion NMOS load
  • Combinational MOS logic circuits with Depletion nMOS Loads
  • Two input NAND and NOR Gate using CMOS logic
  • AOI and OAI complex Logic circuits using CMOS
  • Simple XOR/XNOR function using CMOS logic
  • Complex logic circuits using CMOS logic
  • NOR gate based SR latch using CMOS logic
  • NAND gate based SR latch using CMOS logic
  • Clocked NOR based SR latch using CMOS logic
  • Clocked NOR based JK latch using CMOS logic
  • Clocked NOR based D latch using CMOS logic
Unit 4: FABRICATION OF MOSFET
  • VLSI design flow representation using Y chart
  • Define terms: Hierarchy, Regularity, Modularity, Locality
  • FPGA: Architecture, Characteristics, Advantages, Application and Limitations
  • CMOS Fabrication using CMOS n- Well Process
  • Diffusion
  • Ion implantation
  • Oxidation
  • Photolithography
  • Etching
Unit 5: INTRODUCTION TO VERILOG
  • Basic Features of Verilog HDL
  • Module Definition
  • Data types: wire, reg, constants
  • AND, OR, NOT, XOR, XNOR, NAND and NOR gate implementation using dataflow, structural and behavioural modelling in Verilog
  • Verilog code for Adder and Subtractor circuits : Half Adder, Full Adder, Half Subtractor, Full Subtractor, Full Adder using Half Adder, 4 bit full adder
  • Verilog Programs related to Combinational circuits: Multiplexer and Demultiplexer, Decoder and Encoder, Parity Generator and Parity Checker
  • Test bench: Structure, instantiation of design module in testbench, stimulus generation
  • Use of initial, always and forever blocks in testbench for applying inputs
  • Simple testbench example for Basic gates
  • Verilog programs related to basic Sequential circuits : SR latch, D F/F, T F/F, JK F/F, Parallel Input Parallel Output Shift Register, 4- Bit Binary Up Counter/ Down counter

About this course

Study materials, question papers, and solutions for VLSI System (DI05000021) - Diploma Engineering, Semester 5